From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
To: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
Subject: Re: [libre-riscv-dev] minimum viable ASIC
Date: Fri, 8 May 2020 11:42:57 +0100
Message-ID: <CAPweEDwfqNh-R4EgJP2siEeBZjbqTOZ1svvdk6BBOOuboJeNnA@mail.gmail.com> (raw)
In-Reply-To: <7fcce2dc2715c268c1029783a83ebcd814c489b9.camel@fibraservi.eu>
On Friday, May 8, 2020, Staf Verhaegen <staf@fibraservi.eu> wrote:
>
> Why only 24MHz without PLL ? You should have problems getting external
> clock frequencies up to 100MHz without a problem inside a chip.
>
really? great! and that's driven from an external 100mhz clock? it seems
a little high, i guess i am used to SoCs which all run from a 24mhz XTAL.
l.
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Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-08 9:50 Luke Kenneth Casson Leighton
2020-05-08 10:29 ` Staf Verhaegen
2020-05-08 10:42 ` Luke Kenneth Casson Leighton [this message]
2020-05-08 11:10 ` Staf Verhaegen
2020-05-08 12:43 ` Yehowshua
2020-05-08 12:46 ` Luke Kenneth Casson Leighton
2020-05-08 19:08 ` Staf Verhaegen
2020-05-08 20:35 ` Luke Kenneth Casson Leighton
2020-05-08 12:49 ` Yehowshua
2020-05-08 12:50 ` Yehowshua
2020-05-08 12:59 ` Yehowshua
2020-05-08 12:59 ` Yehowshua
2020-05-08 14:59 ` Luke Kenneth Casson Leighton
2020-05-08 15:00 ` Yehowshua
2020-05-08 15:27 ` [libre-riscv-dev] Debug port (was Re: minimum viable ASIC) whygee
2020-05-08 16:55 ` Luke Kenneth Casson Leighton
2020-05-08 17:23 ` Staf Verhaegen
2020-05-08 22:19 ` Luke Kenneth Casson Leighton
2020-05-20 16:44 ` Staf Verhaegen
2020-05-20 17:22 ` Luke Kenneth Casson Leighton
2020-05-29 10:30 ` Luke Kenneth Casson Leighton
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