[libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V

[bugzilla-daemon@libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=186

--- Comment #97 from Luke Kenneth Casson Leighton <lkcl@lkcl.net> ---
(In reply to Michael Nolan from comment #96)
> (In reply to Luke Kenneth Casson Leighton from comment #95)
> 
> > yes.  however adding a power frontend on it as we found ain't so bad.  can
> > use the same code.
> > 
> > if you look here you can see how basic the test simulator is
> > https://git.libre-riscv.org/?p=soc.git;a=blob;f=src/soc/experiment/score6600.
> > py;h=babce2439233f84c262c08795b873a6167197ec9;hb=HEAD#l859
> > 
> > adjusting that so it uses InternalOp is... er... not hard? :)
> 
> Luke, looks like you and I are doing different things...? It looks to me
> like score6600 is actual hardware, not a simulator.

i'd literally just moved RegSim and MemorySim into their own folder, you put
internalop_sim.py in the same location.

they should be pretty much identical in function.


> I have basic simulator
> I'm working on here
> https://git.libre-riscv.org/?p=soc.git;a=blob;f=src/soc/simulator/
> internalop_sim.py;h=813dd19c40e21283d000fd597074a2cb38595a8a;
> hb=e95b4372c5163bb6f753c92d8445d4af7f117457 - I took some of the elements
> from score6600 (like the register and memory file) and modified them to get
> a basic simulator, which I'm testing along side a real power machine. Were
> you going for something different...?

take a look at sim.py it is near identical to what you did :)

although you have, i think, also added a decoder on it?  so what you wrote can
take actual power instructions, is that right?

sim.py "tracks" what the real hardware does.  so the idea is that after running
the exact same instructions through each, and waiting for the instruction queue
to indicate "no longer busy processing", we can do a memory-memory compare and
a regfile-regfile compare and they should be *exactly* the same.

i wrote a function which does exactly that, one for mem and one for regfile.

unfortunately because this is a multiissue  OoO design we cannot take a
snapshot at a given time and say "yeah this will be exactly the same", you have
to pause, wait for outstanding ops, *then* snapshot.

that "pause" means unfortunately that it affects internal state, because FUs
are emptying rather than being filled with new operations.

but, it is the best we can do.

oh btw, one really important thing to remember: at sone point the sim will do
dynamic SIMD just like in the PartitionedSignal.  code to reuse in
InternalOpSim has already been written... in the PartitionedSignal unit tests!

and, actually, hm, we could probably just lift that code wholesale into a class
then rework the psig unit test to use it, *and* use that same code here.

-- 
You are receiving this mail because:
You are on the CC list for the bug.
_______________________________________________
libre-riscv-dev mailing list
libre-riscv-dev@lists.libre-riscv.org
http://lists.libre-riscv.org/mailman/listinfo/libre-riscv-dev