[libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V

[bugzilla-daemon@libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=186

--- Comment #95 from Luke Kenneth Casson Leighton <lkcl@lkcl.net> ---
(In reply to Michael Nolan from comment #94)

> Yeah, seems reasonable. This wouldn't be cycle accurate or anything right,

well, cycle accurate just means that everything on each clock is exactly as it
would be after one clock

it's actually harder to do a nonaccurate simulator as it involves JIT
translation etc.

cycle accurate means doing TLBs in the simulator, too, and that means we have
something to test the hardware against, there, too.

> just a simulator for our eventual backend?

yes.  however adding a power frontend on it as we found ain't so bad.  can use
the same code.

if you look here you can see how basic the test simulator is
https://git.libre-riscv.org/?p=soc.git;a=blob;f=src/soc/experiment/score6600.py;h=babce2439233f84c262c08795b873a6167197ec9;hb=HEAD#l859

adjusting that so it uses InternalOp is... er... not hard? :)

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