[libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V

[bugzilla-daemon@libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=186

--- Comment #119 from Michael Nolan <mtnolan2640@gmail.com> ---
>coooool.
>
>confirmed able to duplicate that, here.
>
>i did encounter KeyError, register-values not present but it is spurious
>and unreliably occurring.

Huh. It sounds like that's from the register read code, where it reaches in to
a largeish dict to grab the register values. I'll have to see if I can
replicate it on my end.

>
>i added an assert to investigate and, sigh, was no longer seeing failures
>even after running 20 times.
>
>the other really useful addition would be memory-dump / memory location
>reading.

That shouldn't be too hard to add. Similar to the register comparison code,
it'll need to only do it to specific locations as comparing all of memory would
not only take too long, but disagree because qemu loads the kernel and some
other stuff into memory and the simulator does not. 

>btw change of topic, i noticed, just like in the original RegSim, OP_ADD is
>not joined by OP_SUB because Anton chose to do "add1 to op1" as well as
>"invert op1" in the InternalOp csv.
>
>therefore we need to pass the whole of the decode row to the
>execute_alu_sim function, rather than just the enum InternalOp value.

Ah ok.

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