[libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V

[bugzilla-daemon@libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=186

--- Comment #128 from Michael Nolan <mtnolan2640@gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #125)

> hmmm.  if it's a bug in qemu it's one that, i suspect, would have been
> detected
> a loooong time ago.  but... you never know...
> 

> ok so SO (summary overflow), OV (overflow) and OV32 (overflow 32-bit)
> all get set, in XER.  these are listed on p45 3.2.2
> 

Sorry, was actually overflow that I was checking: 
        li 1, 1
        sldi 1, 1, 63
        or 2, 1, 1
        addco. 3, 2, 1
        mfxer 5

That should add -0x80000000000000000 to itself and overflow, and the "o" means
that OV and SO should actually be set. Like I said before, running it in qemu
and reading the xer register gives a result of 0, and reading r5 gives a result
of 0xe0000000.

> however that's not the "carry" flag: that's *CR0*.  which is in... errr...
> the Condition Register p45 2.3.1

It does also list CA and CA32, which should correspond to the flags in xer as
well.

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