[libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V

[bugzilla-daemon@libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=186

--- Comment #120 from Luke Kenneth Casson Leighton <lkcl@lkcl.net> ---
(In reply to Michael Nolan from comment #118)
> (In reply to Luke Kenneth Casson Leighton from comment #116)

> >the other really useful addition would be memory-dump / memory location
> >reading.
> 
> That shouldn't be too hard to add. Similar to the register comparison code,

yes just the right voodoo gdb incantation.  i think it allows byte word dword
selection.

> it'll need to only do it to specific locations as comparing all of memory
> would not only take too long, but disagree because qemu loads the kernel and
> some other stuff into memory and the simulator does not. 

urk :)

> 
> >btw change of topic, i noticed, just like in the original RegSim, OP_ADD is
> >not joined by OP_SUB because Anton chose to do "add1 to op1" as well as
> >"invert op1" in the InternalOp csv.
> >
> >therefore we need to pass the whole of the decode row to the
> >execute_alu_sim function, rather than just the enum InternalOp value.
> 
> Ah ok.

yeh :)

should be very straightforward (you want to do it?) a separate if elif elif,
"if op1.value == Op1.ONE op1 += 1"

can skip carry for now, add as TODO.

then also if row['op1neg'] op1 ^= 0xffffffffffffffff

something like that.

or op1 = (~op1) & 0xffffffffffffffff

that _should_ be sufficient to get sub, subi and neg all working, with not a
lot of effort.

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