[libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V

[bugzilla-daemon@libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=186

--- Comment #94 from Michael Nolan <mtnolan2640@gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #93)
> y'know what, michael... you see in soc experiments comp6600 there is the
> beginnings of a Simulator?
> 
> i have an idea, it might be worthwhile to run with that to its logical
> obvious implication, namely to actually have a simulator, in soc, in python,
> which interprets the InternalOps.
> 
> we then have a reference implementation which we can document properly etc.
> with links to the PDF.
> 
> also it means we have to write the code and so understsnd it.
> 
> speed is not crucial as the nmigen simulator will be screamingly slow. we
> can use cocotb later.
> 
> also at some point we can drop-in power-gem5.
> 
> what does everyone think?

Yeah, seems reasonable. This wouldn't be cycle accurate or anything right, just
a simulator for our eventual backend?

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