From: bugzilla-daemon@libre-riscv.org
To: libre-riscv-dev@lists.libre-riscv.org
Subject: [libre-riscv-dev] [Bug 276] New: SR NAND Latch needed in nmigrn
Date: Fri, 03 Apr 2020 10:00:37 +0000
Message-ID: <bug-276-13@http.bugs.libre-riscv.org/> (raw)
http://bugs.libre-riscv.org/show_bug.cgi?id=276
Bug ID: 276
Summary: SR NAND Latch needed in nmigrn
Product: Libre-SOC's first SoC
Version: unspecified
Hardware: Other
OS: Linux
Status: CONFIRMED
Severity: enhancement
Priority: ---
Component: Source Code
Assignee: lkcl@lkcl.net
Reporter: lkcl@lkcl.net
CC: libre-riscv-dev@lists.libre-riscv.org
NLnet milestone: ---
The Dependency Matrices are huge and need SR NAND latches to get their size
down. This means we need to be able to express them in nmigen, perform some
form of equivalent simulation, and also have them passed through to yosys.
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Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-04-03 10:00 bugzilla-daemon [this message]
2020-04-03 11:00 ` [libre-riscv-dev] [Bug 276] SR NAND Latch needed in nmigen bugzilla-daemon
2020-04-03 12:05 ` bugzilla-daemon
2020-04-03 12:11 ` bugzilla-daemon
2020-04-03 12:52 ` bugzilla-daemon
2020-04-03 13:24 ` bugzilla-daemon
2020-04-03 13:42 ` bugzilla-daemon
2020-04-03 13:58 ` bugzilla-daemon
2020-04-03 14:02 ` bugzilla-daemon
2020-04-03 18:51 ` bugzilla-daemon
2020-04-03 19:21 ` bugzilla-daemon
2020-04-04 8:15 ` bugzilla-daemon
2020-04-04 11:05 ` bugzilla-daemon
2020-04-04 11:10 ` bugzilla-daemon
2020-04-04 11:15 ` bugzilla-daemon
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