[libre-riscv-dev] [Bug 276] SR NAND Latch needed in nmigen

[bugzilla-daemon@libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=276

--- Comment #5 from Luke Kenneth Casson Leighton <lkcl@lkcl.net> ---
(In reply to whitequark from comment #4)
> Ah, there's another option that you might find interesting. Yosys has a
> `$sr` coarse cell. 

yes.  this i _believe_ is what Staf has implemented for us, in the nsxlib
Cell Library:
http://bugs.libre-riscv.org/show_bug.cgi?id=154#c21

> If you're willing to forgo pysim completely and get
> cxxsim working for you, then I could implement support for that cell in
> cxxsim.

yes please.

> It would probably be the least amount of work out of every discussed
> option, provided that you can get cxxsim working for you.

ah then that's worthwhile investigating straight away.  are there examples
anywhere?

> Of course, you might want to look into cxxsim anyway

yes.  we've a half million gate design.  using e.g. cocotb (a python
co-simulator which compiles verilog using verilator and then annotates
and interacts with it from python) was on the cards.

out of interest would that be feasible using cxxsim (either as an addition
to cocotb or as a separate project)?

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