[libre-riscv-dev] [Bug 276] SR NAND Latch needed in nmigen

[bugzilla-daemon@libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=276

--- Comment #4 from whitequark@whitequark.org ---
Ah, there's another option that you might find interesting. Yosys has a `$sr`
coarse cell. If you're willing to forgo pysim completely and get cxxsim working
for you, then I could implement support for that cell in cxxsim. It would
probably be the least amount of work out of every discussed option, provided
that you can get cxxsim working for you.

Of course, you might want to look into cxxsim anyway given the massive
performance improvements it promises (on fully synchronous designs, it's
actually competitive with single-threaded Verilator generated code; on designs
with feedback arcs performance will degrade by the above-mentioned factor of
about 5-10x, but still quite fast.)

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