[libre-riscv-dev] [Bug 276] SR NAND Latch needed in nmigen

[bugzilla-daemon@libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=276

--- Comment #12 from Luke Kenneth Casson Leighton <lkcl@lkcl.net> ---
(In reply to whitequark from comment #11)
> > i presume that given that yosys already has $sr, only nmigen will need  augmenting to produce $sr?
> 
> There's no augmenting necessary. I gave you the code above (the
> `Instance("$sr"...)` that causes nMigen to emit a Yosys `$sr` cell.

fantastic! oh wait - i missed comment 8 (doh - how??)
http://bugs.libre-riscv.org/show_bug.cgi?id=276#c8

ok so the simulation(s) would be what need to recognise that.

could you let me know what amount you'd be happy to receive as a donation
from NLNet, for including $sr in cxxrtl?

also, i appreciate you suggested that we do the exploration, however that
would mean that someone else (other than you) receives money for doing so :)

as we'd very much like to support your work - and because we are a small
team there is such a lot else to do - would you be willing to add a
SRNAND latch example into cxxrtl for example?

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