[libre-riscv-dev] [Bug 276] SR NAND Latch needed in nmigen

[bugzilla-daemon@libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=276

--- Comment #16 from Luke Kenneth Casson Leighton <lkcl@lkcl.net> ---
(In reply to whitequark from comment #15)
> Cxxrtl is upstream in Yosys, including SR latch support.

fantastic, that's really appreciated.  we have *sigh* a bureaucratic
MoU to be signed (4 - now 5 - people waiting on EUR for that one).

not least because of all the other support that you've given, 
and recognising that this is really strategically crucial for us, if
you have time to write a short demo / unit test of the srlatch
i think we can easily justify increasing this one to EUR 300?

(although i'm sure it would be fairly trivial for you to write,
that's because you're most familiar with the code).

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