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From: bugzilla-daemon@libre-riscv.org
To: libre-riscv-dev@lists.libre-riscv.org
Subject: [libre-riscv-dev] [Bug 276] SR NAND Latch needed in nmigen
Date: Fri, 03 Apr 2020 12:11:31 +0000
Message-ID: <bug-276-13-1KSLffStmb@http.bugs.libre-riscv.org/> (raw)
In-Reply-To: <bug-276-13@http.bugs.libre-riscv.org/>

http://bugs.libre-riscv.org/show_bug.cgi?id=276

--- Comment #3 from whitequark@whitequark.org ---
OK, having read that I suggest we follow the standard procedure. The new pysim
design should already handle this kind of logic loop just fine. I suggest you
make a (coarse) SRNAND latch out of normal (coarse) NAND cells, test that it
works correctly in your designs, and if it does not, file an MCVE over at the
nmigen repository. Then I investigate and fix any issues. The same with cxxsim
once it's ready.

Regarding hierarchical design slowdown: this is inevitable in the current pysim
architecture, but cxxsim can trivially use the Yosys flattening functionality
and does not suffer from any hierarchy-related issues.

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  parent reply index

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-04-03 10:00 [libre-riscv-dev] [Bug 276] New: SR NAND Latch needed in nmigrn bugzilla-daemon
2020-04-03 11:00 ` [libre-riscv-dev] [Bug 276] SR NAND Latch needed in nmigen bugzilla-daemon
2020-04-03 12:05 ` bugzilla-daemon
2020-04-03 12:11 ` bugzilla-daemon [this message]
2020-04-03 12:52 ` bugzilla-daemon
2020-04-03 13:24 ` bugzilla-daemon
2020-04-03 13:42 ` bugzilla-daemon
2020-04-03 13:58 ` bugzilla-daemon
2020-04-03 14:02 ` bugzilla-daemon
2020-04-03 18:51 ` bugzilla-daemon
2020-04-03 19:21 ` bugzilla-daemon
2020-04-04  8:15 ` bugzilla-daemon
2020-04-04 11:05 ` bugzilla-daemon
2020-04-04 11:10 ` bugzilla-daemon
2020-04-04 11:15 ` bugzilla-daemon
     [not found] <bug-276-13@https.bugs.libre-soc.org/>
2020-04-10 15:04 ` bugzilla-daemon
2020-04-10 16:16 ` bugzilla-daemon
2020-04-10 17:27 ` bugzilla-daemon

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