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From: bugzilla-daemon@libre-riscv.org
To: libre-riscv-dev@lists.libre-riscv.org
Subject: [libre-riscv-dev] [Bug 276] SR NAND Latch needed in nmigen
Date: Fri, 03 Apr 2020 13:58:51 +0000
Message-ID: <bug-276-13-Tx2f8vY3lM@http.bugs.libre-riscv.org/> (raw)
In-Reply-To: <bug-276-13@http.bugs.libre-riscv.org/>

http://bugs.libre-riscv.org/show_bug.cgi?id=276

--- Comment #7 from Luke Kenneth Casson Leighton <lkcl@lkcl.net> ---
(In reply to whitequark from comment #6)
> > yes.  this i _believe_ is what Staf has implemented for us, in the nsxlib Cell Library: http://bugs.libre-riscv.org/show_bug.cgi?id=154#c21
> 
> If your designs are already using $sr cells then the cxxsim approach would
> be ideal.

brilliant.  at a suitable time in the future we'd need a (quick) indicator
on how to express $sr in nmigen


> > ah then that's worthwhile investigating straight away.  are there examples anywhere?
> 
> Yes, in the pull request introducing the backend (which is not yet merged,
> I'm adding some polish to it right now):
> https://github.com/YosysHQ/yosys/pull/1562. The examples are a bit sparse
> but I think the developers working on this project will have no issues
> figuring things out

correct :)

> (or just ask me).
> 
> The general idea behind cxxsim is to be as straightforward translation of
> RTLIL to C++ as possible. Of course, RTLIL is not imperative, so some extra
> logic is necessary.
> 
> This extra logic isn't something I invented myself, but rather I took the
> well-known VHDL two-phase simulator that provides deterministic* results
> regardless of evaluation order, even for combinatorial loops, and adapted it
> to RTLIL. Some VHDL developers call it "the crown jewel of VHDL" and I
> concur, it is an excellent algorithm.

i heard rumour about this from elsewhere.

> > out of interest would that be feasible using cxxsim (either as an addition
> > to cocotb or as a separate project)?
> 
> So, I'm working on two different patches, which are somewhat confusingly
> named "cxxrtl" and "cxxsim".

:)

> For now I suggest that you simulate your code using a C++ testbench to see
> what sort of performance you get, and running simple acceptanace tests to
> see if there are any glaring issues in cxxrtl that break your design. 

willdo.

> I
> think there is no point writing code to integrate cxxrtl with cocotb; cxxsim
> is about as much effort, and will let you use your exiting testcases
> unmodified.

fantastic.

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  parent reply index

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-04-03 10:00 [libre-riscv-dev] [Bug 276] New: SR NAND Latch needed in nmigrn bugzilla-daemon
2020-04-03 11:00 ` [libre-riscv-dev] [Bug 276] SR NAND Latch needed in nmigen bugzilla-daemon
2020-04-03 12:05 ` bugzilla-daemon
2020-04-03 12:11 ` bugzilla-daemon
2020-04-03 12:52 ` bugzilla-daemon
2020-04-03 13:24 ` bugzilla-daemon
2020-04-03 13:42 ` bugzilla-daemon
2020-04-03 13:58 ` bugzilla-daemon [this message]
2020-04-03 14:02 ` bugzilla-daemon
2020-04-03 18:51 ` bugzilla-daemon
2020-04-03 19:21 ` bugzilla-daemon
2020-04-04  8:15 ` bugzilla-daemon
2020-04-04 11:05 ` bugzilla-daemon
2020-04-04 11:10 ` bugzilla-daemon
2020-04-04 11:15 ` bugzilla-daemon
     [not found] <bug-276-13@https.bugs.libre-soc.org/>
2020-04-10 15:04 ` bugzilla-daemon
2020-04-10 16:16 ` bugzilla-daemon
2020-04-10 17:27 ` bugzilla-daemon

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