[libre-riscv-dev] [Bug 314] Create Condition Register pipeline

[bugzilla-daemon@libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=314

--- Comment #13 from Michael Nolan <mtnolan2640@gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #9)
> ugh, ugh.
> 
> i have a horrible feeling about "undefined" behaviour.  we need to properly
> investigate and find out exactly what happens during that "undefined"
> behaviour by running native assembler on the TALOS-II workstation, with
> a full range of FXM bits (only 256 instructions), and a random set of
> CR and RS (times 256).
> 
> this will tell us exactly what happens.

Qemu seems to do nothing when it's not onehot
        lis 1, 0xdead
        ori 1, 1, 0xbeef # r1 = 0xdeadbeef
        lis 2, 0x1234 
        ori 2, 2, 0x5678 # r2 = 0x12345678
        mtcr 1           # cr = 0xdeadbeef
        mtcrf 0xf, 2     
        mfcr 3           # r3 should be 0xdead5678
        mtcr 1           # cr = 0xdeadbeef again
        # mtocrf 0xf, 2
        .byte 0x7c, 0x50, 0xf1, 0x20
        mfcr 4           # who knows

(gdb) p/x $r3
$1 = 0xdead5678
(gdb) p/x $r4
$2 = 0xdeadbeef

-- 
You are receiving this mail because:
You are on the CC list for the bug.
_______________________________________________
libre-riscv-dev mailing list
libre-riscv-dev@lists.libre-riscv.org
http://lists.libre-riscv.org/mailman/listinfo/libre-riscv-dev