[libre-riscv-dev] [Bug 314] Create Condition Register pipeline

[bugzilla-daemon@libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=314

--- Comment #9 from Luke Kenneth Casson Leighton <lkcl@lkcl.net> ---
ugh, ugh.

i have a horrible feeling about "undefined" behaviour.  we need to properly
investigate and find out exactly what happens during that "undefined"
behaviour by running native assembler on the TALOS-II workstation, with
a full range of FXM bits (only 256 instructions), and a random set of
CR and RS (times 256).

this will tell us exactly what happens.

my concern is that if we rely on the "undefined" behaviour to say "ok we
choose to make mtcrf and mtocrf the same", some assembly writers may
have chosen *specifically* to assume that CR is set to ZERO (or some
other value) after noting that that behaviour occurs on POWER9...

you follow where that goes?

i really do not like "undefined" behaviour in specifications.  it's always
a problem.

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