[libre-riscv-dev] [Bug 314] Create Condition Register pipeline

[bugzilla-daemon@libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=314

--- Comment #14 from Luke Kenneth Casson Leighton <lkcl@lkcl.net> ---
(In reply to Michael Nolan from comment #12)

> We can do this for crand and friends, as well as mcrf, but it doesn't work
> for mtcrf or mfcr because they can read or write the whole cr register

ah good catch.  updated.  yes you're right.  this would be where the "multi-bit
hazard" detection would come into play.  the bit-vector would be

0   1   ... 7   8
CR0 CR1 ... CR7 {ALLCRs}

for crand the decoding of BA (etc) would set the corresponding CR register
hazard *and* on vector bit 8 {ALLCRs}... but not the other bits.

thus it would be possible to have multiple parallel overlapping crand(s) (etc)
as long as the read/write dependencies on CR0-CR7 do not clash

however mtcrf would set bit 8 {ALLCRs} *AND* it would set *ALL* other bits 0
thru 7.

as it's an optimisation it's off the TODO list for now.

-- 
You are receiving this mail because:
You are on the CC list for the bug.
_______________________________________________
libre-riscv-dev mailing list
libre-riscv-dev@lists.libre-riscv.org
http://lists.libre-riscv.org/mailman/listinfo/libre-riscv-dev