From: bugzilla-daemon@libre-soc.org
To: libre-riscv-dev@lists.libre-riscv.org
Subject: [libre-riscv-dev] [Bug 314] Create POWER9 Condition Register pipeline
Date: Sat, 23 May 2020 01:25:48 +0000
Message-ID: <bug-314-13-Qg7lYTRzhW@https.bugs.libre-soc.org/> (raw)
In-Reply-To: <bug-314-13@https.bugs.libre-soc.org/>
https://bugs.libre-soc.org/show_bug.cgi?id=314
--- Comment #17 from Luke Kenneth Casson Leighton <lkcl@lkcl.net> ---
https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/fu/cr/pipe_data.py;h=2894144fd814444a7bdb75ae6c695af8519ae084;hb=HEAD
can add b to CRInputData.
https://libre-soc.org/openpower/isa/fixedtrap/
what on earth isel is doing in the trap instruction group is beyond me. could
be i just put the pseudocode in the wrong file
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Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-15 15:33 [libre-riscv-dev] [Bug 314] New: Create " bugzilla-daemon
2020-05-15 15:33 ` [libre-riscv-dev] [Bug 314] " bugzilla-daemon
2020-05-15 15:33 ` bugzilla-daemon
2020-05-15 15:41 ` bugzilla-daemon
2020-05-15 21:53 ` bugzilla-daemon
2020-05-15 22:05 ` bugzilla-daemon
2020-05-16 18:00 ` bugzilla-daemon
2020-05-16 18:27 ` bugzilla-daemon
2020-05-16 18:28 ` bugzilla-daemon
2020-05-16 18:38 ` bugzilla-daemon
2020-05-16 18:38 ` bugzilla-daemon
2020-05-16 18:42 ` bugzilla-daemon
2020-05-16 18:46 ` bugzilla-daemon
2020-05-16 18:47 ` bugzilla-daemon
2020-05-16 19:30 ` bugzilla-daemon
2020-05-16 20:07 ` bugzilla-daemon
2020-05-16 20:30 ` bugzilla-daemon
2020-05-16 22:06 ` bugzilla-daemon
2020-05-16 22:11 ` bugzilla-daemon
2020-05-16 22:14 ` bugzilla-daemon
2020-05-19 18:08 ` bugzilla-daemon
2020-05-23 1:17 ` [libre-riscv-dev] [Bug 314] Create POWER9 " bugzilla-daemon
2020-05-23 1:21 ` bugzilla-daemon
2020-05-23 1:25 ` bugzilla-daemon [this message]
2020-05-23 10:36 ` bugzilla-daemon
2020-05-23 20:30 ` bugzilla-daemon
2020-05-23 21:01 ` bugzilla-daemon
2020-05-24 13:11 ` bugzilla-daemon
2020-05-24 19:57 ` bugzilla-daemon
2020-05-24 20:47 ` bugzilla-daemon
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