[libre-riscv-dev] [Bug 314] Create POWER9 Condition Register pipeline - bugzilla-daemon

From: bugzilla-daemon@libre-soc.org
To: libre-riscv-dev@lists.libre-riscv.org
Subject: [libre-riscv-dev] [Bug 314] Create POWER9 Condition Register pipeline
Date: Sat, 23 May 2020 01:21:18 +0000
Message-ID: <bug-314-13-smk6CSIkts@https.bugs.libre-soc.org/> (raw)
In-Reply-To: <bug-314-13@https.bugs.libre-soc.org/>

https://bugs.libre-soc.org/show_bug.cgi?id=314

--- Comment #16 from Luke Kenneth Casson Leighton <lkcl@lkcl.net> ---
hmmmm there are not many good choices for putting this instruction in.  it
requires RA RC INT regs, and full CR's BI field as input.

for output it needs INT RS

CR is the closest least disruptive candidate, if a 2nd INT reg is added: RB.

    when OP_ISEL =>
        crbit := to_integer(unsigned(insn_bc(e_in.insn)));
        if e_in.cr(31-crbit) = '1' then
            result := a_in;
        else
            result := b_in;
        end if;
        result_en := '1';

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