[libre-riscv-dev] [Bug 314] Create Condition Register pipeline

[bugzilla-daemon@libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=314

--- Comment #3 from Michael Nolan <mtnolan2640@gmail.com> ---
The hell? IBM separately defines mtcrf and mtocrf, and reserves a bit to
differentiate between the two. Except there's no functional difference between
the two that I can tell, and the assembler will even assemble some instances of
mtcrf as mtocrf. 


Basically mtcrf fxm, reg uses fxm to construct a 32 bit mask, where each bit in
fxm corresponds to 4 bits in the mask (so mtcrf 0xf1 would correspond to a mask
of 0xffff000f). It then uses this mask to choose between bits of CR and the
input register, and writes them back to CR

mtocrf fxm, reg assumes fxm is a one hot encoded index into the bits of reg. It
grabs those bits from reg and inserts them into cr, leaving the rest untouched.
If fxm is not onehot, then the result is undefined.

Why these are different, I don't know.

-- 
You are receiving this mail because:
You are on the CC list for the bug.
_______________________________________________
libre-riscv-dev mailing list
libre-riscv-dev@lists.libre-riscv.org
http://lists.libre-riscv.org/mailman/listinfo/libre-riscv-dev