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From: Yehowshua <yimmanuel3@gatech.edu>
To: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
Subject: Re: [libre-riscv-dev] Understanding the LibreSOC core
Date: Mon, 8 Jun 2020 15:14:05 -0400
Message-ID: <9D061BD0-3FD9-4A05-A070-745C82482CAF@gatech.edu> (raw)
In-Reply-To: <878934CF-C5C0-40DA-8299-140ADD4EAA79@gatech.edu>



> On Jun 8, 2020, at 2:58 PM, Yehowshua <yimmanuel3@gatech.edu> wrote:
> 
> Those look like reasonable numbers.
> 
> I think it should fit. At minimum, I can get it running
> inside the LiteX Verilator environment.
> 

Also do keep in mind that LiteX **requires the CPU to 
initialize the DDR3 present on the Versa.

Two ways to approach this:
1. I can strip the LiteX BIOS down to bare essentials for initializing DDR3 on the Versa, and the build that.
Once built, I can comb through the assembled binary looking for any instructions we don’t 
currently support.
2. We can use SDR on the ulx3s which requires no CPU intervention.

Yehowshua


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  parent reply index

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-06-08 18:03 Sanjay Menon
2020-06-08 18:24 ` Luke Kenneth Casson Leighton
2020-06-08 18:46   ` Yehowshua
2020-06-08 18:55     ` Luke Kenneth Casson Leighton
2020-06-08 18:58       ` Yehowshua
2020-06-08 19:01         ` Sanjay Menon
2020-06-08 19:09           ` Yehowshua
2020-06-08 19:14         ` Yehowshua [this message]
2020-06-08 20:38           ` Luke Kenneth Casson Leighton
2020-06-08 20:46             ` Luke Kenneth Casson Leighton
2020-06-08 21:19             ` Michael Nolan
2020-06-08 22:17               ` Luke Kenneth Casson Leighton
2020-06-08 22:18                 ` Luke Kenneth Casson Leighton
2020-06-08 20:11       ` Michael Nolan
2020-06-08 20:12         ` Yehowshua
2020-06-08 20:31           ` Luke Kenneth Casson Leighton
2020-06-08 19:02     ` Luke Kenneth Casson Leighton
2020-06-08 19:05       ` Yehowshua

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