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From: Sanjay Menon <sanjayamenon.mec@gmail.com>
To: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
Subject: Re: [libre-riscv-dev] Understanding the LibreSOC core
Date: Tue, 9 Jun 2020 00:31:07 +0530
Message-ID: <CAE_rhwbBd5Y9=TgbpWNsu+S5Yxm4VeVvrdHCNKNcE3gk4B3Dmg@mail.gmail.com> (raw)
In-Reply-To: <878934CF-C5C0-40DA-8299-140ADD4EAA79@gatech.edu>

Thanks for replying Luke.Would be looking into some of the things you
mentioned.

Yehowshua, if it does not fit you could try Partial dynamic reconfiguration
:)

Regards,
Sanjay

On Tue, 9 Jun 2020, 00:28 Yehowshua, <yimmanuel3@gatech.edu> wrote:

> Those look like reasonable numbers.
>
> I think it should fit. At minimum, I can get it running
> inside the LiteX Verilator environment.
>
> Yehowshua
>
> _______________________________________________
> libre-riscv-dev mailing list
> libre-riscv-dev@lists.libre-riscv.org
> http://lists.libre-riscv.org/mailman/listinfo/libre-riscv-dev
>
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  reply index

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-06-08 18:03 Sanjay Menon
2020-06-08 18:24 ` Luke Kenneth Casson Leighton
2020-06-08 18:46   ` Yehowshua
2020-06-08 18:55     ` Luke Kenneth Casson Leighton
2020-06-08 18:58       ` Yehowshua
2020-06-08 19:01         ` Sanjay Menon [this message]
2020-06-08 19:09           ` Yehowshua
2020-06-08 19:14         ` Yehowshua
2020-06-08 20:38           ` Luke Kenneth Casson Leighton
2020-06-08 20:46             ` Luke Kenneth Casson Leighton
2020-06-08 21:19             ` Michael Nolan
2020-06-08 22:17               ` Luke Kenneth Casson Leighton
2020-06-08 22:18                 ` Luke Kenneth Casson Leighton
2020-06-08 20:11       ` Michael Nolan
2020-06-08 20:12         ` Yehowshua
2020-06-08 20:31           ` Luke Kenneth Casson Leighton
2020-06-08 19:02     ` Luke Kenneth Casson Leighton
2020-06-08 19:05       ` Yehowshua

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