Re: [libre-riscv-dev] Understanding the LibreSOC core

[Luke Kenneth Casson Leighton <lkcl@lkcl.net>]

On Mon, Jun 8, 2020 at 8:14 PM Yehowshua <yimmanuel3@gatech.edu> wrote:
>
>
>
> > On Jun 8, 2020, at 2:58 PM, Yehowshua <yimmanuel3@gatech.edu> wrote:
> >
> > Those look like reasonable numbers.
> >
> > I think it should fit. At minimum, I can get it running
> > inside the LiteX Verilator environment.
> >
>
> Also do keep in mind that LiteX **requires the CPU to
> initialize the DDR3 present on the Versa.

microwatt i believe did something like that (recently).

> Two ways to approach this:
> 1. I can strip the LiteX BIOS down to bare essentials for initializing DDR3 on the Versa, and then build that.

there's a BIOS??  oink :)

if there's a BIOS, it means that at least some instructions can be
loaded (into something - probably an on-board SRAM) and executed, and
that at least means we can test _something_ before getting to that
stage.

(meaning: the instructions to initialise DDR3 have to execute _from_
somewhere, they can't be executed from thin air)

btw we were planning to put in a "Board Support Package" NLNet Grant Request.

l.

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