From: Jacob Lifshay <programmerjake@gmail.com>
To: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
Subject: Re: [libre-riscv-dev] little-endian only power cores and spec compliance
Date: Tue, 12 May 2020 00:46:22 -0700
Message-ID: <CAC2bXD4ko6A1P9omroZSMq0YjYzyShAr5D05csQw1aDh3-eNOw@mail.gmail.com> (raw)
In-Reply-To: <CAC2bXD5SkgmjEi7TgqNMDc1gtkxzJFpNJn3ZfkFYsvAYgBzbcA@mail.gmail.com>
On Tue, May 12, 2020, 00:40 Jacob Lifshay <programmerjake@gmail.com> wrote:
> On Tue, May 12, 2020, 00:32 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
> wrote:
>
>>
>> without BE, this is flat-out impossible to do.
>>
>
> Oops, forgot about that.
>
Never mind, now that I take more than 15s to think about it, we need BE for
the instruction stream but LE for data access (since that's effectively
industry standard), so it's still effectively a LE-only architecture since
everything but the instruction decoder is LE, but the instruction decoder
can be switched to BE mode.
Having our architecture require BE for all memory accesses just because we
want to support 16-bit instructions is a non-starter in my opinion
Jacob
>
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Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-12 7:24 Jacob Lifshay
2020-05-12 7:31 ` Luke Kenneth Casson Leighton
2020-05-12 7:40 ` Jacob Lifshay
2020-05-12 7:46 ` Jacob Lifshay [this message]
2020-05-12 8:07 ` Luke Kenneth Casson Leighton
2020-05-12 8:23 ` Luke Kenneth Casson Leighton
2020-05-13 1:22 ` [libre-riscv-dev] [OpenPOWER-HDL-Cores] " Hugh Blemings
2020-05-13 1:41 ` Benjamin Herrenschmidt
2020-05-13 9:11 ` Luke Kenneth Casson Leighton
2020-05-13 2:27 ` [libre-riscv-dev] " Jacob Lifshay
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