From: Jacob Lifshay <programmerjake@gmail.com>
To: openpower-hdl-cores@mailinglist.openpowerfoundation.org
Cc: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
Subject: Re: [libre-riscv-dev] little-endian only power cores and spec compliance
Date: Tue, 12 May 2020 19:27:26 -0700
Message-ID: <CAC2bXD6oAs8hGpLAtM4NJq2ifSsu-wLeCmO6=GtRMNWzPjoR6w@mail.gmail.com> (raw)
In-Reply-To: <CAC2bXD6LVtrMh7RT=11ZVypujcJRaMokG7XuBwF87veBiMMDLQ@mail.gmail.com>
On Tue, May 12, 2020, 00:24 Jacob Lifshay <programmerjake@gmail.com> wrote:
> Over on Libre-SOC's mailing list (CCed), we've been having a conversation
> about the newly-released spec v3.1 and the compliance levels:
> http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-May/006502.html
>
> we are building a cpu that is intended to be Linux capable, however
> doesn't support Power's SIMD instructions and is LE only. We've been
> running into an issue with the spec's compliance levels:
>
It turns out that I spoke too soon about what exactly Libre-SOC's CPU will
support, I apologise.
With that said, I still think it would be useful for OpenPower to support
LE-only processors without the additional requirements imposed by the Linux
and AIX compatibility levels.
Jacob
>
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Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-12 7:24 Jacob Lifshay
2020-05-12 7:31 ` Luke Kenneth Casson Leighton
2020-05-12 7:40 ` Jacob Lifshay
2020-05-12 7:46 ` Jacob Lifshay
2020-05-12 8:07 ` Luke Kenneth Casson Leighton
2020-05-12 8:23 ` Luke Kenneth Casson Leighton
2020-05-13 1:22 ` [libre-riscv-dev] [OpenPOWER-HDL-Cores] " Hugh Blemings
2020-05-13 1:41 ` Benjamin Herrenschmidt
2020-05-13 9:11 ` Luke Kenneth Casson Leighton
2020-05-13 2:27 ` Jacob Lifshay [this message]
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