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From: Hugh Blemings <hugh@blemings.org>
To: Jacob Lifshay <programmerjake@gmail.com>,
	openpower-hdl-cores@mailinglist.openpowerfoundation.org
Cc: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
Subject: Re: [libre-riscv-dev] [OpenPOWER-HDL-Cores] little-endian only power cores and spec compliance
Date: Wed, 13 May 2020 11:22:01 +1000
Message-ID: <ec667579-06e2-ff44-4604-b160149feaa3@blemings.org> (raw)
In-Reply-To: <CAC2bXD6LVtrMh7RT=11ZVypujcJRaMokG7XuBwF87veBiMMDLQ@mail.gmail.com>

Hi All,

I'm barely qualified to add much more than $0.20 to this thread, but 
will give it a whirl...

I've not had a chance to dig into the v3.1 spec as yet but can offer the 
observation that the intent (as demonstrated in the Microwatt 
implementation for example) was that the simpler/simplest 
implementations would be LE with BE optional. SIMD also optional in 
these as well.

So if the docs don't represent this we'll need to take a closer look :)

We're getting more of the key folk from our member companies (mostly 
IBM) into the loop through this list but as Luke rightly pointed out 
over on libre-riscv-dev they're a busy crew at the moment with a new 
chip due out soon :)

That said I imagine someone will chime in soon who -actually- knows this 
stuff!

Cheers,
Hugh

(Speaking for myself only in this case, though I believe wearing my ED 
hat I'd be saying much the same :)


On 12/5/20 5:24 pm, Jacob Lifshay wrote:
> Over on Libre-SOC's mailing list (CCed), we've been having a 
> conversation about the newly-released spec v3.1 and the compliance 
> levels:
> http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-May/006502.html
>
> we are building a cpu that is intended to be Linux capable, however 
> doesn't support Power's SIMD instructions and is LE only. We've been 
> running into an issue with the spec's compliance levels:
> the linux compliance level requires SIMD and BE is optional but the 
> lower compliance levels require BE but SIMD is optional.
>
> Would it be possible to get a LE version of the int and int+float 
> compliance levels added to the spec?
>
> Other ideas also welcome
>
> Jacob Lifshay
>
> _______________________________________________
> OpenPOWER-HDL-Cores mailing list
> OpenPOWER-HDL-Cores@mailinglist.openpowerfoundation.org
> http://lists.mailinglist.openpowerfoundation.org/mailman/listinfo/openpower-hdl-cores
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  parent reply index

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-05-12  7:24 [libre-riscv-dev] " Jacob Lifshay
2020-05-12  7:31 ` Luke Kenneth Casson Leighton
2020-05-12  7:40   ` Jacob Lifshay
2020-05-12  7:46     ` Jacob Lifshay
2020-05-12  8:07       ` Luke Kenneth Casson Leighton
2020-05-12  8:23         ` Luke Kenneth Casson Leighton
2020-05-13  1:22 ` Hugh Blemings [this message]
2020-05-13  1:41   ` [libre-riscv-dev] [OpenPOWER-HDL-Cores] " Benjamin Herrenschmidt
2020-05-13  9:11     ` Luke Kenneth Casson Leighton
2020-05-13  2:27 ` [libre-riscv-dev] " Jacob Lifshay

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