Re: [libre-riscv-dev] [OpenPOWER-HDL-Cores] little-endian only power cores and spec compliance

From: Benjamin Herrenschmidt <benh@ozlabs.org>
To: Hugh Blemings <hugh@blemings.org>,
	Jacob Lifshay <programmerjake@gmail.com>,
	 openpower-hdl-cores@mailinglist.openpowerfoundation.org
Cc: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
Subject: Re: [libre-riscv-dev] [OpenPOWER-HDL-Cores] little-endian only power cores and spec compliance
Date: Wed, 13 May 2020 11:41:00 +1000
Message-ID: <ba6dfcfcac4cb37dab95ba1669f68f57f01347d1.camel@ozlabs.org> (raw)
In-Reply-To: <ec667579-06e2-ff44-4604-b160149feaa3@blemings.org>

On Wed, 2020-05-13 at 11:22 +1000, Hugh Blemings wrote:
> Hi All,
> I'm barely qualified to add much more than $0.20 to this thread, but
> will give it a whirl...
> I've not had a chance to dig into the v3.1 spec as yet but can offer
> the observation that the intent (as demonstrated in the Microwatt
> implementation for example) was that the simpler/simplest
> implementations would be LE with BE optional. SIMD also optional in
> these as well.

The main difficulty is that in practice, a powerpc64le toolchain will
generate code with both FP and SIMD instructions. I don't think it's
possible to generate a fully soft-float one and even if you managed
with gcc, glibc somewhat assumes it too. At least from memory.

If OpenPower wants to go down a path more similar to RiscV here and
support small(er) implementations, it's necessary to stop having the
toolchain engineers push for only supporting the latest/greatest IBM
server CPUs :-)

The Microwatt core is now starting to boot Linux as well (not merged
yet) but at the moment this requires some kernel hacks to work around
the above, such as plumbing in FPU emulation, and I know Paul has
issues generating a usable userspace...

> So if the docs don't represent this we'll need to take a closer look
> :)
> We're getting more of the key folk from our member companies (mostly
> IBM) into the loop through this list but as Luke rightly pointed out
> over on libre-riscv-dev they're a busy crew at the moment with a new
> chip due out soon :)
> That said I imagine someone will chime in soon who -actually- knows
> this stuff!
> Cheers,
> Hugh
> (Speaking for myself only in this case, though I believe wearing my
> ED hat I'd be saying much the same :)
> 
> On 12/5/20 5:24 pm, Jacob Lifshay wrote:
> > Over on Libre-SOC's mailing list (CCed), we've been having a
> > conversation about the newly-released spec v3.1 and the compliance
> > levels:
> > 
http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-May/006502.html
> > 
> > we are building a cpu that is intended to be Linux capable, however
> > doesn't support Power's SIMD instructions and is LE only. We've
> > been running into an issue with the spec's compliance levels:
> > the linux compliance level requires SIMD and BE is optional but the
> > lower compliance levels require BE but SIMD is optional.
> > 
> > Would it be possible to get a LE version of the int and int+float
> > compliance levels added to the spec?
> > 
> > Other ideas also welcome
> > 
> > Jacob Lifshay
> > 
> > 
> > _______________________________________________
> > OpenPOWER-HDL-Cores mailing list
> > OpenPOWER-HDL-Cores@mailinglist.openpowerfoundation.org
> > 
http://lists.mailinglist.openpowerfoundation.org/mailman/listinfo/openpower-hdl-cores
> 
> _______________________________________________
> OpenPOWER-HDL-Cores mailing list
> OpenPOWER-HDL-Cores@mailinglist.openpowerfoundation.org
> 
http://lists.mailinglist.openpowerfoundation.org/mailman/listinfo/openpower-hdl-cores

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