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From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
To: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
Subject: Re: [libre-riscv-dev] little-endian only power cores and spec compliance
Date: Tue, 12 May 2020 09:23:52 +0100
Message-ID: <CAPweEDwhaqqcEbqkAKk3ASeemQBZ==5LPBZcq6nEeWOQ-mxtow@mail.gmail.com> (raw)
In-Reply-To: <CAPweEDx2w25Wx0_quaJyNz87nXPVwDs3RyQh-aiOkk0LHcSMkg@mail.gmail.com>

so, jacob: under the libre-soc charter, there's a part that says
"mistakes and merit belong to those who make it".  this means that
it's your responsibility to write to opencores-hdl-discuss to correct
the mistaken impression about BE/LE.

can i recommend:

* doing it very soon (so that they don't spend needless precious time)
* keeping it short, and
* also letting them know that we're still discussing and will get back
to them with a carefully-considered consensus response?

l.

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Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-05-12  7:24 Jacob Lifshay
2020-05-12  7:31 ` Luke Kenneth Casson Leighton
2020-05-12  7:40   ` Jacob Lifshay
2020-05-12  7:46     ` Jacob Lifshay
2020-05-12  8:07       ` Luke Kenneth Casson Leighton
2020-05-12  8:23         ` Luke Kenneth Casson Leighton [this message]
2020-05-13  1:22 ` [libre-riscv-dev] [OpenPOWER-HDL-Cores] " Hugh Blemings
2020-05-13  1:41   ` Benjamin Herrenschmidt
2020-05-13  9:11     ` Luke Kenneth Casson Leighton
2020-05-13  2:27 ` [libre-riscv-dev] " Jacob Lifshay

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