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From: Jacob Lifshay <programmerjake@gmail.com>
To: openpower-hdl-cores@mailinglist.openpowerfoundation.org
Cc: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
Subject: [libre-riscv-dev] little-endian only power cores and spec compliance
Date: Tue, 12 May 2020 00:24:35 -0700
Message-ID: <CAC2bXD6LVtrMh7RT=11ZVypujcJRaMokG7XuBwF87veBiMMDLQ@mail.gmail.com> (raw)

Over on Libre-SOC's mailing list (CCed), we've been having a conversation
about the newly-released spec v3.1 and the compliance levels:
http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-May/006502.html

we are building a cpu that is intended to be Linux capable, however doesn't
support Power's SIMD instructions and is LE only. We've been running into
an issue with the spec's compliance levels:
the linux compliance level requires SIMD and BE is optional but the lower
compliance levels require BE but SIMD is optional.

Would it be possible to get a LE version of the int and int+float
compliance levels added to the spec?

Other ideas also welcome

Jacob Lifshay
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Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-05-12  7:24 Jacob Lifshay [this message]
2020-05-12  7:31 ` Luke Kenneth Casson Leighton
2020-05-12  7:40   ` Jacob Lifshay
2020-05-12  7:46     ` Jacob Lifshay
2020-05-12  8:07       ` Luke Kenneth Casson Leighton
2020-05-12  8:23         ` Luke Kenneth Casson Leighton
2020-05-13  1:22 ` [libre-riscv-dev] [OpenPOWER-HDL-Cores] " Hugh Blemings
2020-05-13  1:41   ` Benjamin Herrenschmidt
2020-05-13  9:11     ` Luke Kenneth Casson Leighton
2020-05-13  2:27 ` [libre-riscv-dev] " Jacob Lifshay

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