From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
To: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
Subject: Re: [libre-riscv-dev] little-endian only power cores and spec compliance
Date: Tue, 12 May 2020 08:31:17 +0100
Message-ID: <CAPweEDyUuFwL1yjyHESQEAVxQ3bLqN1VWcUS1enXTv6UN_3t8g@mail.gmail.com> (raw)
In-Reply-To: <CAC2bXD6LVtrMh7RT=11ZVypujcJRaMokG7XuBwF87veBiMMDLQ@mail.gmail.com>
(removing opencores-hdl cc)
we need BE because without BE it is not possible to support VBLOCK,
Compressed or SVPrefix.
with BE, the opcode is presented in the first 2 bytes of any
instruction stream, regardless of whether it is 32-bit, VB, C or SVP,
and consequently the major opcodes that we plan to overload will
always be in the first 2 bytes and can reliably be used to detect the
mode.
without BE, this is flat-out impossible to do.
it would have been good to wait until we had agreed what to say on
that list because it is populated by extremely busy people whom we now
need to inform (implicitly or explicitly) that we've not discussed
properly and now their extremely precious time has to be taken up with
a correction.
can i suggest that we set some interaction guidelines for opencores-hdl?
l.
On Tue, May 12, 2020 at 8:24 AM Jacob Lifshay <programmerjake@gmail.com> wrote:
>
> Over on Libre-SOC's mailing list (CCed), we've been having a conversation
> about the newly-released spec v3.1 and the compliance levels:
> http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-May/006502.html
>
> we are building a cpu that is intended to be Linux capable, however doesn't
> support Power's SIMD instructions and is LE only. We've been running into
> an issue with the spec's compliance levels:
> the linux compliance level requires SIMD and BE is optional but the lower
> compliance levels require BE but SIMD is optional.
>
> Would it be possible to get a LE version of the int and int+float
> compliance levels added to the spec?
>
> Other ideas also welcome
>
> Jacob Lifshay
> _______________________________________________
> libre-riscv-dev mailing list
> libre-riscv-dev@lists.libre-riscv.org
> http://lists.libre-riscv.org/mailman/listinfo/libre-riscv-dev
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Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-12 7:24 Jacob Lifshay
2020-05-12 7:31 ` Luke Kenneth Casson Leighton [this message]
2020-05-12 7:40 ` Jacob Lifshay
2020-05-12 7:46 ` Jacob Lifshay
2020-05-12 8:07 ` Luke Kenneth Casson Leighton
2020-05-12 8:23 ` Luke Kenneth Casson Leighton
2020-05-13 1:22 ` [libre-riscv-dev] [OpenPOWER-HDL-Cores] " Hugh Blemings
2020-05-13 1:41 ` Benjamin Herrenschmidt
2020-05-13 9:11 ` Luke Kenneth Casson Leighton
2020-05-13 2:27 ` [libre-riscv-dev] " Jacob Lifshay
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