From: Jacob Lifshay <programmerjake@gmail.com>
To: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
Subject: [libre-riscv-dev] effects of powered-off chip sections on current leakage
Date: Sat, 13 Jun 2020 22:06:18 -0700
Message-ID: <CAC2bXD64OBzL_-gaxipwyCR5NqgphuJmtmK1woTE9mWqpE1r8A@mail.gmail.com> (raw)
In-Reply-To: <bug-376-13-VsIxQBkNqh@https.bugs.libre-soc.org/>
On Fri, Jun 12, 2020, 17:21 <bugzilla-daemon@libre-soc.org> wrote:
> https://bugs.libre-soc.org/show_bug.cgi?id=376
>
> --- Comment #24 from Luke Kenneth Casson Leighton <lkcl@lkcl.net> ---
> (In reply to Jacob Lifshay from comment #23)
> > (In reply to Luke Kenneth Casson Leighton from comment #21)
> > > (In reply to Jacob Lifshay from comment #19)
> > > > > > Also, it might be worthwhile to add one more
> > > > > > core and disable one at manufacture time as a way to increase
> yield.
> > > > >
> > > > > that's a good idea. have to bear in mind that current leakage
> occurs
> > > > > regardless of whether the silicon is in use or not.
> > > >
> > > > If we set up each core as a different power domain (which will also
> help
> > > > with idle power), the disabled core could be powered-down.
> > >
> > > (you still get current leakage even when powered down, is my point)
> >
> > I meant something like having a mosfet in the power line to the whole
> core,
> > so the entire power supply could be turned off. Assuming that mosfet
> wasn't
> > garbage, the power usage for the whole core could be reduced to the
> > microwatt level.
>
> apologies: you're still not getting it. even the *existence* of the gates,
> even when fully powered down, with zero oower connected in any way, shape
> or
> form, *still* causes not insignificant current leakage.
>
Please explain in more detail, perhaps with some supporting references --
it still makes close to zero sense to me how additional unused silicon area
could affect the rest of the chip, since that area itself couldn't be
drawing any power since all wires into it that are at 0V due to the power
rails and I/O signals being switched off.
> this shows up particularly badly in the design of GSM ASICs. thousands of
> correlators are required to get an initial lock within "seconds" expected
> by
> users... or... and then they are "powered down" exactly as you suggest.
>
> unfortunately even their very existence, even powered down, causes current
> leakage, adversely affecting power consumption and draining battery life.
>
> the solution had to involve "A-GPS" where the LAT/LONG (or even just one of
> those) was obtained from the bearest celltower. this reduced the
> correlator
> search soace to the point where a decent DSP could handle the job instead.
>
neat! didn't know about A-GPS before, though I assumed it was related to
GPS somehow.
>
Jacob
>
_______________________________________________
libre-riscv-dev mailing list
libre-riscv-dev@lists.libre-riscv.org
http://lists.libre-riscv.org/mailman/listinfo/libre-riscv-dev
next prev parent reply index
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-12 13:30 [libre-riscv-dev] [Bug 376] New: Assess 40/45 nm 2022 target and interfaces bugzilla-daemon
2020-06-12 13:31 ` [libre-riscv-dev] [Bug 376] " bugzilla-daemon
2020-06-12 13:52 ` bugzilla-daemon
2020-06-12 15:14 ` bugzilla-daemon
2020-06-12 15:27 ` bugzilla-daemon
2020-06-12 16:17 ` bugzilla-daemon
2020-06-12 16:29 ` bugzilla-daemon
2020-06-12 17:26 ` bugzilla-daemon
2020-06-12 17:34 ` bugzilla-daemon
2020-06-12 17:44 ` bugzilla-daemon
2020-06-12 18:00 ` bugzilla-daemon
2020-06-12 18:01 ` bugzilla-daemon
2020-06-12 18:08 ` bugzilla-daemon
2020-06-12 18:13 ` bugzilla-daemon
2020-06-12 21:51 ` bugzilla-daemon
2020-06-12 21:52 ` bugzilla-daemon
2020-06-12 22:00 ` bugzilla-daemon
2020-06-12 22:05 ` bugzilla-daemon
2020-06-12 22:19 ` bugzilla-daemon
2020-06-12 22:32 ` bugzilla-daemon
2020-06-12 22:55 ` bugzilla-daemon
2020-06-12 23:02 ` bugzilla-daemon
2020-06-12 23:11 ` bugzilla-daemon
2020-06-12 23:14 ` bugzilla-daemon
2020-06-13 0:20 ` bugzilla-daemon
2020-06-14 5:06 ` Jacob Lifshay [this message]
2020-06-14 11:30 ` [libre-riscv-dev] effects of powered-off chip sections on current leakage Luke Kenneth Casson Leighton
2020-06-14 20:07 ` Jacob Lifshay
2020-06-14 22:08 ` Cesar Strauss
2020-06-13 3:37 ` [libre-riscv-dev] [Bug 376] Assess 40/45 nm 2022 target and interfaces bugzilla-daemon
2020-06-14 17:27 ` bugzilla-daemon
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=CAC2bXD64OBzL_-gaxipwyCR5NqgphuJmtmK1woTE9mWqpE1r8A@mail.gmail.com \
--to=programmerjake@gmail.com \
--cc=libre-riscv-dev@lists.libre-riscv.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Libre RISC-V Mailing list Archives (accessible via public-inbox)
Archives are clonable: git clone --mirror https://inbox.libre-soc.org/libre-riscv-dev
Example config snippet for mirrors
AGPL code for this site: git clone https://public-inbox.org/public-inbox.git