[libre-riscv-dev] [Bug 376] Assess 40/45 nm 2022 target and interfaces

[bugzilla-daemon@libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=376

--- Comment #25 from Luke Kenneth Casson Leighton <lkcl@lkcl.net> ---
i took a look at the OPENCAPI PDF on the proposed interfaces.  IBM put OpenCAPI
2 was on top of 8x PCIe 4.0

the later slides, blacked out, show rhat POWER7 was in 40nm.

later, by the time they move to 25GBit/s, they are for POWER9 which is in 14nm.

this, in conjunction with the power requirements, basically tells us that there
is an unachievable mismatch between 25.6 Gbit/s SERDES and a 40/45nm target.

if we were instead to target 14nm or below, we could achieve a 25 GBit/s SERDES
PHY.

this however would require that, as our first major production chip, we seek a
minimum of USD 20 million funding.

if however we stick to PCIe @ 3200 mhz, this *is* achievable in 40/45nm.  with
sufficient lanes it becomes possible to reach the bandwidth required, and to
not expect investors to take a huge risk on an unproven team.


alternatively, we stick with plain DDR3/4 because it is also achievable, but
expensive and timeconsuming (SymbioticEDA: 8 to 12 months fulltime work on a
PHY, USD 600,000).

alternatively, we use multiple HyperRAM interfaces and overclock the protocol,
connecting to a suitable FPGA that either has a DDR3/4 interface *or* suitable
SERDES sufficient to do OpenCAPI.  the ECP5G springs to mind although its DRAM
interface is only capable of 200mhz (400mhz DDR).

the advantage of a 3200 mhz SERDES is that it is useful for a large number of
things that rely on a PCIe PHY.  OpenCAPI, HMC, and PCIe itself.

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