Libre RISC-V Mailing list Archives (accessible via public-inbox)
 help / color / Atom feed
From: bugzilla-daemon@libre-soc.org
To: libre-riscv-dev@lists.libre-riscv.org
Subject: [libre-riscv-dev] [Bug 376] Assess 40/45 nm 2022 target and interfaces
Date: Fri, 12 Jun 2020 16:29:04 +0000
Message-ID: <bug-376-13-I2ksk97o6i@https.bugs.libre-soc.org/> (raw)
In-Reply-To: <bug-376-13@https.bugs.libre-soc.org/>

https://bugs.libre-soc.org/show_bug.cgi?id=376

--- Comment #6 from Cole Poirier <colepoirier@gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #5)
> correct.  this is what the original quad core was intended for.
[snip]
> thus, only 1x 32 bit DDR 800 mhz RAM interface would be perfectly
> sufficient... for *that* scenario (hence the $4 target price), and it would
> only need around a 350mW power budget (the DRAMs themselves, that is.  the
> SoC DRAM drivers would i *think* be around an additional 150mW. have to
> check).

Thanks for this clarification, helps a lot for understanding our product's (or
now products' ?) market segmentation.

> the target being discussed here, by virtue of having interfaces that at full
> speed consume an estimated 8 watts, these are far outside a
> tablet/smartphone 100 million+ volumes power budget.
> 
> it is basically a radically different market: GPU Graphics Card market,
> basically.

Oh, that also makes a lot more sense. Kanban will definitely help me keep track
of and make sense of these related but separate 'tracks'.
> 
> *if correct*, with the (unconfirmed, anticipated) higher power demands, a
> plastic package is in no way going to be adequate.
> 
> it will have to be ceramic, with a metal top.  i'd also suggest a minimum 25
> mm square, to help with thermal dissipation.
> 
> the actual pincount, due to the SERDES, might be quite reasonable (except
> there's a lot of them): maybe 400 to 500 or so.
> 
> we will need people who know exactly what they are doing, here, who have
> done this type of high power high speed ASIC before.
> 
> Rudi is the person who springs to mind, not just from the technical
> capability and 25+ years experience, he also likes what we are doing.
> 
> we need some numbers.

Wow that is radically different, and very, very exciting! I'm gladdened to hear
of Rudy's experience as well as his affinity towards our project. Is it
possible that he may know some other people that would be interested in either
assisting him, or working on another part of the project?  Of course receiving
donations for all of their completed tasks. Or if we are able to find some more
investors, we can pay them for new project requirements that are not covered
under the scope of our existing NLNET 2018 and 2019 grants?

-- 
You are receiving this mail because:
You are on the CC list for the bug.
_______________________________________________
libre-riscv-dev mailing list
libre-riscv-dev@lists.libre-riscv.org
http://lists.libre-riscv.org/mailman/listinfo/libre-riscv-dev

  parent reply index

Thread overview: 31+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-06-12 13:30 [libre-riscv-dev] [Bug 376] New: " bugzilla-daemon
2020-06-12 13:31 ` [libre-riscv-dev] [Bug 376] " bugzilla-daemon
2020-06-12 13:52 ` bugzilla-daemon
2020-06-12 15:14 ` bugzilla-daemon
2020-06-12 15:27 ` bugzilla-daemon
2020-06-12 16:17 ` bugzilla-daemon
2020-06-12 16:29 ` bugzilla-daemon [this message]
2020-06-12 17:26 ` bugzilla-daemon
2020-06-12 17:34 ` bugzilla-daemon
2020-06-12 17:44 ` bugzilla-daemon
2020-06-12 18:00 ` bugzilla-daemon
2020-06-12 18:01 ` bugzilla-daemon
2020-06-12 18:08 ` bugzilla-daemon
2020-06-12 18:13 ` bugzilla-daemon
2020-06-12 21:51 ` bugzilla-daemon
2020-06-12 21:52 ` bugzilla-daemon
2020-06-12 22:00 ` bugzilla-daemon
2020-06-12 22:05 ` bugzilla-daemon
2020-06-12 22:19 ` bugzilla-daemon
2020-06-12 22:32 ` bugzilla-daemon
2020-06-12 22:55 ` bugzilla-daemon
2020-06-12 23:02 ` bugzilla-daemon
2020-06-12 23:11 ` bugzilla-daemon
2020-06-12 23:14 ` bugzilla-daemon
2020-06-13  0:20 ` bugzilla-daemon
2020-06-14  5:06   ` [libre-riscv-dev] effects of powered-off chip sections on current leakage Jacob Lifshay
2020-06-14 11:30     ` Luke Kenneth Casson Leighton
2020-06-14 20:07       ` Jacob Lifshay
2020-06-14 22:08         ` Cesar Strauss
2020-06-13  3:37 ` [libre-riscv-dev] [Bug 376] Assess 40/45 nm 2022 target and interfaces bugzilla-daemon
2020-06-14 17:27 ` bugzilla-daemon

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=bug-376-13-I2ksk97o6i@https.bugs.libre-soc.org/ \
    --to=bugzilla-daemon@libre-soc.org \
    --cc=libre-riscv-dev@lists.libre-riscv.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link

Libre RISC-V Mailing list Archives (accessible via public-inbox)

Archives are clonable: git clone --mirror https://inbox.libre-soc.org/libre-riscv-dev

Example config snippet for mirrors


AGPL code for this site: git clone https://public-inbox.org/public-inbox.git