[libre-riscv-dev] [Bug 376] Assess 40/45 nm 2022 target and interfaces

[bugzilla-daemon@libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=376

--- Comment #15 from Luke Kenneth Casson Leighton <lkcl@lkcl.net> ---
Yehowshua writes, "Some notes from my conversation with Michael":

>> from the ecp5 note on the serdes
>>   - "3.2 Gbps operation with low 85
>>  mW power per channel”
>
> Ok
> hmm
> channel i say 1rx or 1tx?
>
>> 1 tx/rx pair
>
>
> so 8 pairs at 3.2Gbps is about a watt
> Can't imagine for 25Gbps
>
>> Oh, and ecp5 is a 40nm chip
>> so it should be comparable to ours
>
>
> that’s what I’m afraid of
>
>
>> they might be targeting a different subprocess
>> than us though. I think most fabs offer the
>> options of like "low power", "high performance”,
>>  or "high density"
>
>> and I suspect ours will need to be less flexible than the ecp5's so that might save us some power

-- 
You are receiving this mail because:
You are on the CC list for the bug.
_______________________________________________
libre-riscv-dev mailing list
libre-riscv-dev@lists.libre-riscv.org
http://lists.libre-riscv.org/mailman/listinfo/libre-riscv-dev