[libre-riscv-dev] microwatt feature request: "switch off all optimisations" mode

[libre-riscv-dev] microwatt feature request: "switch off all optimisations" mode

[Luke Kenneth Casson Leighton]

paul, benjamin, mikey: i have a huge favour to ask of you (or a "howto"
question), given that i never done VHDL programming before.

thank to florent of enjoy-digital's help, libresoc now has connectivity to
litex in simulation, just like in microwatt.  in particular he added a
"Display" option on any wishbone activity requested by (either) core,
allowing me to see what is going on.

i was therefore looking to do cycle-accurate side by side comparisons, spot
the discrepancies, fix the bug and move on to the next one.

this technique has worked extremely well up to now by comparing against
qemu, and against our python simulator.

we would like to be able to add microwatt to that list.

the problem is that microwatt has branch prediction, L1 cacheing and
pipeline latency all of which mean that i am completely guessing about what
caused any given bus read/write.

any kind of side-by-side comparison of log files, looking for the "one
instruction that does something different/wrong" is out of the question.

... *unless*... there is a "mode" for microwatt that is effectively
equivalent to gdb single-step.

we need a way to stop microwatt from doing any kind of overlapping
instructions.  this *may* be possible already through the JTAG/debug
interface, i do not know.

the alternative is some minor modifications that throw in a deliberate 10
to 20 cycle delay in the instruction issue phase.  this would give ample
time to inspect the internal state (regfiles, PC, SPRs, etc) looking for
discrepancies when running the exact same binary.

what would you suggest here? how can we "single-step" microwatt?  clearly
performance is not important: cycle-accurate comparisons is the goal.

with thanks, and understanding that you are busy people,

l.



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Re: [libre-riscv-dev] microwatt feature request: "switch off all optimisations" mode

[Luke Kenneth Casson Leighton]

On Friday, July 31, 2020, Luke Kenneth Casson Leighton <lkcl@lkcl.net>
wrote:

>
> what would you suggest here? how can we "single-step" microwatt?  clearly
> performance is not important: cycle-accurate comparisons is the goal.
>

i since realised that the DMI interface serves this purpose, and
investigated core_debug.vhdl

with a little bit (or a lot) of futzing about with a FSM i should be able
to run a single instruction then cycle through all of the GPRs, PC and MSR,
dumping them out.

by implementing the same interface in libresoc i can do a cycle by cycle
comparison and find the discrepancies.

it would be particularly useful to be able to get at the SPRs and the CR as
well, this way.

is there a standard for DMI address bus locations?

l



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Re: [libre-riscv-dev] [OpenPOWER-HDL-Cores] microwatt feature request: "switch off all optimisations" mode

[Herrenschmidt, Benjamin]

On Sat, 2020-08-01 at 14:55 +0100, Luke Kenneth Casson Leighton wrote:
> 
> 
> On Friday, July 31, 2020, Luke Kenneth Casson Leighton <lkcl@lkcl.net
> > wrote:
> > what would you suggest here? how can we "single-step" microwatt? 
> > clearly performance is not important: cycle-accurate comparisons is
> > the goal.
> > 
> 
> i since realised that the DMI interface serves this purpose, and
> investigated core_debug.vhdl
>  
> with a little bit (or a lot) of futzing about with a FSM i should be
> able to run a single instruction then cycle through all of the GPRs,
> PC and MSR, dumping them out.
> 
> by implementing the same interface in libresoc i can do a cycle by
> cycle comparison and find the discrepancies.
> 
> it would be particularly useful to be able to get at the SPRs and the
> CR as well, this way.
> 
> is there a standard for DMI address bus locations?

Not really... I just made it all up :-)

Cheers,
Ben.

> l 
> 
> 
> 
> _______________________________________________
> OpenPOWER-HDL-Cores mailing list
> OpenPOWER-HDL-Cores@mailinglist.openpowerfoundation.org
> 
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Re: [libre-riscv-dev] microwatt feature request: "switch off all optimisations" mode

[Luke Kenneth Casson Leighton]

On Monday, August 3, 2020, Herrenschmidt, Benjamin <benh@amazon.com> wrote:

>
> > is there a standard for DMI address bus locations?
>
> Not really... I just made it all up :-)


that's funny, i like it :)

can we collaborate on making some more up, for example adding CR, XER and
the remaining SPRs to the list of registers?

also bear in mind, FP regs may get added (to microwatt).  and that in
libresoc we intend to expand the scalar int and fp regs to 128 entries.

l.



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Re: [libre-riscv-dev] [OpenPOWER-HDL-Cores] microwatt feature request: "switch off all optimisations" mode

[Benjamin Herrenschmidt]

On Mon, 2020-08-03 at 02:00 +0100, Luke Kenneth Casson Leighton wrote:
> 
> 
> On Monday, August 3, 2020, Herrenschmidt, Benjamin <benh@amazon.com>
> wrote:
> > > is there a standard for DMI address bus locations?
> > 
> > Not really... I just made it all up :-)
> 
> that's funny, i like it :)
> 
> can we collaborate on making some more up, for example adding CR, XER
> and the remaining SPRs to the list of registers?

Sure. Patches welcome ;-) Also check out Paul's WIP branches, he also
occasionally add stuff.

> also bear in mind, FP regs may get added (to microwatt).  and that in
> libresoc we intend to expand the scalar int and fp regs to 128
> entries.

Paul has some of that in his FPU work already.

Cheers,
Ben.



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Re: [libre-riscv-dev] microwatt feature request: "switch off all optimisations" mode

[Luke Kenneth Casson Leighton]

On Monday, August 3, 2020, Benjamin Herrenschmidt <benh@kernel.crashing.org>
wrote:

> On Mon, 2020-08-03 at 02:00 +0100, Luke Kenneth Casson Leighton wrote:
> >
> >
> > On Monday, August 3, 2020, Herrenschmidt, Benjamin <benh@amazon.com>
> > wrote:
> > > > is there a standard for DMI address bus locations?
> > >
> > > Not really... I just made it all up :-)
> >
> > that's funny, i like it :)
> >
> > can we collaborate on making some more up, for example adding CR, XER
> > and the remaining SPRs to the list of registers?
>
> Sure. Patches welcome ;-)


ah i was thinking more along the lines of agreeing a spec that suits both
teams, even if the definitions are reserved for later implementation.

(btw we've an october tapeout deadline and i am not yet a vhdl developer).

by agreeing a set of registers, future teams with their own implementation
will want to save development effort and conform to the same spec.


Also check out Paul's WIP branches, he also
> occasionally add stuff.


willdo.



>
> > also bear in mind, FP regs may get added (to microwatt).  and that in
> > libresoc we intend to expand the scalar int and fp regs to 128
> > entries.
>
> Paul has some of that in his FPU work already.


ah excellent.




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Re: [libre-riscv-dev] [OpenPOWER-HDL-Cores] microwatt feature request: "switch off all optimisations" mode

[Herrenschmidt, Benjamin]

On Mon, 2020-08-03 at 02:35 +0100, Luke Kenneth Casson Leighton wrote:
> 
> ah i was thinking more along the lines of agreeing a spec that suits
> both teams, even if the definitions are reserved for later
> implementation.

That's fine, the patch could be adding a debug-regs-spec.txt :-)

(Or we could use a .h as a spec, and use it in mw_debug)

Cheers,
Ben.

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Re: [libre-riscv-dev] microwatt feature request: "switch off all optimisations" mode

[Luke Kenneth Casson Leighton]

On Monday, August 3, 2020, Herrenschmidt, Benjamin <benh@amazon.com> wrote:

> On Mon, 2020-08-03 at 02:35 +0100, Luke Kenneth Casson Leighton wrote:
> >
> > ah i was thinking more along the lines of agreeing a spec that suits
> > both teams, even if the definitions are reserved for later
> > implementation.
>
> That's fine, the patch could be adding a debug-regs-spec.txt :-)


that works :)


>
> (Or we could use a .h as a spec, and use it in mw_debug)


understood.

l.



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