From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
To: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
Subject: Re: [libre-riscv-dev] memory interface diagram woes
Date: Tue, 28 Apr 2020 15:26:29 +0100
Message-ID: <CAPweEDwaLg3UCF_P+KLDRmUpfYFZf==AKKrevE+g24ytpWiYDw@mail.gmail.com> (raw)
In-Reply-To: <365bd897eff6a78ed70f9c07a60c8c4e@f-cpu.org>
On Tue, Apr 28, 2020 at 2:33 PM <whygee@f-cpu.org> wrote:
>
> On 2020-04-28 13:56, Luke Kenneth Casson Leighton wrote:
> > fail. on to version *12*. it's about 90 minutes to draw and verify
> > each diagram.
>
> have a look at http://www.falstad.com/circuit/circuitjs.html
> it has some digital simulation capabilities, and lets you
> exchange the designs with simple minified links.
oooo i looove it.
https://github.com/sharpie7/circuitjs1
another one, circuitdiagram
https://github.com/circuitdiagram/circuitdiagram
> Then you can integrate digital (sub-)circuits as IFRAMEs
> in webpages to explain and expose the principles of your design.
> It's not the very best system but it's incredibly useful
> and flexible. You won't use DIA anymore ;-)
that's a great idea.
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Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-04-23 6:49 Jacob Lifshay
2020-04-23 9:02 ` Luke Kenneth Casson Leighton
2020-04-23 10:29 ` Luke Kenneth Casson Leighton
2020-04-23 14:37 ` Luke Kenneth Casson Leighton
2020-04-26 12:27 ` Luke Kenneth Casson Leighton
2020-04-27 6:06 ` Jacob Lifshay
2020-04-27 10:07 ` Luke Kenneth Casson Leighton
2020-04-27 10:25 ` Luke Kenneth Casson Leighton
2020-04-27 12:38 ` Luke Kenneth Casson Leighton
[not found] ` <CAPweEDwtjksKH3odd0gfeBbLhVVPm=KD3auoihJq4X+-ROOg6g@mail.gmail.com>
2020-04-28 13:33 ` whygee
2020-04-28 14:26 ` Luke Kenneth Casson Leighton [this message]
2020-04-28 14:38 ` Jacob Lifshay
2020-04-28 14:43 ` Luke Kenneth Casson Leighton
2020-04-28 14:53 ` [libre-riscv-dev] circuitjs Jacob Lifshay
2020-04-28 15:03 ` Luke Kenneth Casson Leighton
2020-04-28 15:10 ` Jacob Lifshay
2020-04-28 15:35 ` Luke Kenneth Casson Leighton
2020-04-28 19:37 ` [libre-riscv-dev] HTTaP and Design for Test (was Re: circuitjs) whygee
2020-04-28 19:10 ` [libre-riscv-dev] circuitjs whygee
2020-04-28 15:28 ` [libre-riscv-dev] memory interface diagram woes Luke Kenneth Casson Leighton
2020-04-28 16:30 ` Luke Kenneth Casson Leighton
2020-04-29 15:10 ` Luke Kenneth Casson Leighton
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