Re: [libre-riscv-dev] memory interface diagram woes

[Luke Kenneth Casson Leighton <lkcl@lkcl.net>]

https://libre-soc.org/3d_gpu/ld_st_comp_unit.jpg

okaaaaay, finally.  (btw don't tell no-one i watch American Ninja
Warrior re-runs whilst drawing these).

there's three modes:

* LD mode - OP1 READ, OP2 WRITE, memory read
* LD-UPDATE mode - OP1 READ *and* WRITE, OP2 WRITE
* ST mode - OP1 READ, OP2 READ, memory write

notes:

* ALU and ADR latch covers the case where the Adder only triggers
"result ok" for 1 cycle, latching the output EA (effective address)
indefinitely, where ALU-SR's job is to signal that the address is
ready.  the two separate latches are because you musn't de-latch the
address from the LD/ST-Port just because GoAddr acknowledgement
occurred

* likewise LD-sr latches on "LD_OK" and captures the LD Data output
from the LD/ST-Port, where the WR-sr latch reacts differently.  i am
not entirely certain that two separate latches are needed here, to be
honest, however i believe it is "safe" to have them separate.

* SHADOW_N stops all write activity until it is *definitely* known
that the possibility for exceptions has passed.  this is *the* reason
why we can do a full O-o-O design with "precise exceptions": something
that the "Academic" literature does *NOT* recognise as being possible
with a 6600-style architecture.

l.

_______________________________________________
libre-riscv-dev mailing list
libre-riscv-dev@lists.libre-riscv.org
http://lists.libre-riscv.org/mailman/listinfo/libre-riscv-dev