From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
To: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
Subject: Re: [libre-riscv-dev] memory interface diagram woes
Date: Wed, 29 Apr 2020 16:10:10 +0100
Message-ID: <CAPweEDy5Zm-e=pOfUt9o7DTEutc1hv1iK=AENE+du+ypvZMV5Q@mail.gmail.com> (raw)
In-Reply-To: <CAPweEDxr-xS_1WHa4U=-MkErRCdX_BCY4Rgvh+2XH8msmwmyJg@mail.gmail.com>
oh god! POWER LD/ST has an indexed version and an immediate version
of instructions! so that's *eight* possible variants:
* LD/ST
* Update y/n
* Immediate/Indexed
fortunately i have the logic for an immediate-or-OP2 already drawn out.
this is getting ridiculous! :)
l.
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Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-04-23 6:49 Jacob Lifshay
2020-04-23 9:02 ` Luke Kenneth Casson Leighton
2020-04-23 10:29 ` Luke Kenneth Casson Leighton
2020-04-23 14:37 ` Luke Kenneth Casson Leighton
2020-04-26 12:27 ` Luke Kenneth Casson Leighton
2020-04-27 6:06 ` Jacob Lifshay
2020-04-27 10:07 ` Luke Kenneth Casson Leighton
2020-04-27 10:25 ` Luke Kenneth Casson Leighton
2020-04-27 12:38 ` Luke Kenneth Casson Leighton
[not found] ` <CAPweEDwtjksKH3odd0gfeBbLhVVPm=KD3auoihJq4X+-ROOg6g@mail.gmail.com>
2020-04-28 13:33 ` whygee
2020-04-28 14:26 ` Luke Kenneth Casson Leighton
2020-04-28 14:38 ` Jacob Lifshay
2020-04-28 14:43 ` Luke Kenneth Casson Leighton
2020-04-28 14:53 ` [libre-riscv-dev] circuitjs Jacob Lifshay
2020-04-28 15:03 ` Luke Kenneth Casson Leighton
2020-04-28 15:10 ` Jacob Lifshay
2020-04-28 15:35 ` Luke Kenneth Casson Leighton
2020-04-28 19:37 ` [libre-riscv-dev] HTTaP and Design for Test (was Re: circuitjs) whygee
2020-04-28 19:10 ` [libre-riscv-dev] circuitjs whygee
2020-04-28 15:28 ` [libre-riscv-dev] memory interface diagram woes Luke Kenneth Casson Leighton
2020-04-28 16:30 ` Luke Kenneth Casson Leighton
2020-04-29 15:10 ` Luke Kenneth Casson Leighton [this message]
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