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From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
To: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
Subject: Re: [libre-riscv-dev] memory interface diagram woes
Date: Thu, 23 Apr 2020 15:37:32 +0100
Message-ID: <CAPweEDxFAhwD6ZNw=Oq-dF3jicgnRAumoKRr6E5u-E-z5=+_GA@mail.gmail.com> (raw)
In-Reply-To: <CAPweEDzzfQ3PHgc40PnZrs+KxBovFp+gYEBEV7TjiJ8SGJfLrw@mail.gmail.com>

illustration, jacob.

with 8 LDST FUs, each with 2 64-bit data ports, how will those 16
entries be inserted into MemoryQueue?
https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/memory_pipe_experiment/memory_queue.py;hb=HEAD

as in, not so much "how" (because in "coding terms" it's a "simple"
matter of writing the code).

i mean "how many wires will be required in order to multiplex up to
16x simultaneous 64-bit chunks into the same (one) MemoryQueue"?

l.

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Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-04-23  6:49 Jacob Lifshay
2020-04-23  9:02 ` Luke Kenneth Casson Leighton
2020-04-23 10:29   ` Luke Kenneth Casson Leighton
2020-04-23 14:37     ` Luke Kenneth Casson Leighton [this message]
2020-04-26 12:27 ` Luke Kenneth Casson Leighton
2020-04-27  6:06   ` Jacob Lifshay
2020-04-27 10:07     ` Luke Kenneth Casson Leighton
2020-04-27 10:25       ` Luke Kenneth Casson Leighton
2020-04-27 12:38         ` Luke Kenneth Casson Leighton
     [not found]           ` <CAPweEDwtjksKH3odd0gfeBbLhVVPm=KD3auoihJq4X+-ROOg6g@mail.gmail.com>
2020-04-28 13:33             ` whygee
2020-04-28 14:26               ` Luke Kenneth Casson Leighton
2020-04-28 14:38                 ` Jacob Lifshay
2020-04-28 14:43                   ` Luke Kenneth Casson Leighton
2020-04-28 14:53                     ` [libre-riscv-dev] circuitjs Jacob Lifshay
2020-04-28 15:03                       ` Luke Kenneth Casson Leighton
2020-04-28 15:10                         ` Jacob Lifshay
2020-04-28 15:35                           ` Luke Kenneth Casson Leighton
2020-04-28 19:37                             ` [libre-riscv-dev] HTTaP and Design for Test (was Re: circuitjs) whygee
2020-04-28 19:10                       ` [libre-riscv-dev] circuitjs whygee
2020-04-28 15:28                     ` [libre-riscv-dev] memory interface diagram woes Luke Kenneth Casson Leighton
2020-04-28 16:30                       ` Luke Kenneth Casson Leighton
2020-04-29 15:10                         ` Luke Kenneth Casson Leighton

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