From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
To: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
Subject: Re: [libre-riscv-dev] memory interface diagram woes
Date: Mon, 27 Apr 2020 13:38:26 +0100
Message-ID: <CAPweEDz5bGnjGJB2aE8GsKBSPOjNRP5dDRhyJe1D6MtZzqMMNQ@mail.gmail.com> (raw)
In-Reply-To: <CAPweEDwO1QBtCCbip-vo4NOi5ZV73kNwMm-S3BSBrcRGfQ+JPQ@mail.gmail.com>
scream! 2 days writing out the 10th version of the logic-diagram for
LD/ST in 12 months, only to note that POWER has a 2-in 2-out variant
of LD called "update" which optionally puts the computed Effective
Address out on RA as a 2nd write source!
fortunately i can i believe cookie-cut an existing diagram
(https://libre-soc.org/3d_gpu/architecture/6600scoreboard/600x-compunit_multi_rw.jpg)
this contains multi-write protection already however the difference is
that it needs to switch between single-write and dual-write. i think i
can do that by "fake" setting one of the SR Latches to "already
acknowledged".
patience, patience...
l.
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Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-04-23 6:49 Jacob Lifshay
2020-04-23 9:02 ` Luke Kenneth Casson Leighton
2020-04-23 10:29 ` Luke Kenneth Casson Leighton
2020-04-23 14:37 ` Luke Kenneth Casson Leighton
2020-04-26 12:27 ` Luke Kenneth Casson Leighton
2020-04-27 6:06 ` Jacob Lifshay
2020-04-27 10:07 ` Luke Kenneth Casson Leighton
2020-04-27 10:25 ` Luke Kenneth Casson Leighton
2020-04-27 12:38 ` Luke Kenneth Casson Leighton [this message]
[not found] ` <CAPweEDwtjksKH3odd0gfeBbLhVVPm=KD3auoihJq4X+-ROOg6g@mail.gmail.com>
2020-04-28 13:33 ` whygee
2020-04-28 14:26 ` Luke Kenneth Casson Leighton
2020-04-28 14:38 ` Jacob Lifshay
2020-04-28 14:43 ` Luke Kenneth Casson Leighton
2020-04-28 14:53 ` [libre-riscv-dev] circuitjs Jacob Lifshay
2020-04-28 15:03 ` Luke Kenneth Casson Leighton
2020-04-28 15:10 ` Jacob Lifshay
2020-04-28 15:35 ` Luke Kenneth Casson Leighton
2020-04-28 19:37 ` [libre-riscv-dev] HTTaP and Design for Test (was Re: circuitjs) whygee
2020-04-28 19:10 ` [libre-riscv-dev] circuitjs whygee
2020-04-28 15:28 ` [libre-riscv-dev] memory interface diagram woes Luke Kenneth Casson Leighton
2020-04-28 16:30 ` Luke Kenneth Casson Leighton
2020-04-29 15:10 ` Luke Kenneth Casson Leighton
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