[libre-riscv-dev] [Bug 216] LOAD STORE buffer needed

[bugzilla-daemon@libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=216

--- Comment #37 from Luke Kenneth Casson Leighton <lkcl@lkcl.net> ---
(In reply to Jacob Lifshay from comment #34)
> What do you think of the idea to write a single-op-at-a-time memory
> interface with all the caches & stuff to work with the rest of the SoC?

as intermediary steps this is a good idea.   the code i wrote yesterday already
does exactly that (and is why i did it. it "works". performance sucks.)

however stopping at a level that does not meet the requirements of keeping
those twin 128 bit L1 caches fully occupied on every cycle is not.



> it will be much simpler to get right and not take as much time, then, after
> that works, we can work on the much more complex multi-op version. That way,
> we will have something that works even if the multi-op version doesn't end
> up working in time for the october tape out.

yes.

although it will suck.

strictly speaking just as in minerva if you look at the code there exists
"cache bypassed" LoadStore code.

by using that code directly we also have the option to switch off the L1 cache,
making unit testing much easier.

and to emphasise, again (i have mentioned this about four times but have not
received a response), the minerva L1 code and associates LDST compiletime
reconfigureable Interface does *not* need duplicating.  it is good enough as-is
and can simply be expanded to 64 bit then quqdrupled up, or expanded to 128 bit
and doubled up, and 128 to 64 bit Wishbone Arbiters dropped on the front.

with only needing to connect to two well defined interfaces (multiple
PortInterfaces on one side and multiple minerva LDSTCache interfaces on the
other) this task is much simpler and straightforward than it seems.

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