[libre-riscv-dev] [Bug 216] LOAD STORE buffer needed

[bugzilla-daemon@libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=216

--- Comment #33 from Luke Kenneth Casson Leighton <lkcl@lkcl.net> ---
okaaay, it's messy but functional, and, importantly, illustrates the API,
jacob.

i've not put in actual LD/ST width yet, so the tests "pass" based on storing
a 16-bit value into a hard-coded-16-bit-wide "Memory", the important thing
is the signalling and API conformance, illustrating the timing that's
required (and expected) by LDSTCompUnit.

at least this allows me to move on to the (new, ridiculously-redrawn)
LDSTCompUnit.

we'll need to coordinate when it comes to adding twin ports (for misaligned)
however it may just be ok there to assume the misaligned port is never
used by LDSTCompUnit as the 2nd port is being added to L0CacheBuffer, get
the unit tests working for L0CacheBuffer, then add it to LDSTCompUnit, and
*then* add unit tests to LDSTCompUnit that try using it.

-- 
You are receiving this mail because:
You are on the CC list for the bug.
_______________________________________________
libre-riscv-dev mailing list
libre-riscv-dev@lists.libre-riscv.org
http://lists.libre-riscv.org/mailman/listinfo/libre-riscv-dev