[libre-riscv-dev] [Bug 216] LOAD STORE buffer needed

[bugzilla-daemon@libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=216

--- Comment #47 from Luke Kenneth Casson Leighton <lkcl@lkcl.net> ---
hi tobias, saw the latest commit, getting there.

------
            comb, sync = m.d.comb, m.d.sync

sync is not needed


-------
            #(1) pick a row
            m.submodules.pick = pick = PriorityEncoder(self.array_size)
            for j in range(self.array_size):
                with m.If(self.addr_match_i[j].bool()):
                    pick.i.eq(pick.i||(1<<j))

again: as previous comment, this is not python (and the comb += is missing
at the front, which means that the nmigen AST is discarded, doing nothing)

everything is parallel hardware, not sequential python.  the nmigen AST
captures that parallel hardware definition.

so, here, we want each bit of the PriorityPicker input to connect to one
bit of the test of whether a line in addr_match_i is empty/non-empty.
therefore, we need to assign addr_match_i[i].bool() to each bit of pick.i:

            # assign each priority-picker input bit the test whether the
            # address match line is non-empty.
            for j in range(self.array_size):
                comb += pick.i[j].eq(self.addr_match_i[j].bool())

simple as that.



-------
            self.data_o.eq(ortreereduce(l))


import is missing.


-----

fix those and it'll be time to move on to a unit test.

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