[libre-riscv-dev] [Bug 216] LOAD STORE buffer needed

[bugzilla-daemon@libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=216

--- Comment #24 from Luke Kenneth Casson Leighton <lkcl@lkcl.net> ---
i just realised something:

* misaligned LD/STs will create a pair of LD/STs (on each FU) where it
  is *guaranteed* that Addr[4] for the LO-HI request will be mutually
  exclusive.  if Addr[4] is 0 for the LO request of the pair, Addr[4]
  is *guaranteed* to be 1 for the HI request of the pair

* therefore splitting into L0 left/right LO/HI isn't going to work...
  unless we accept that the LO/HI requests actually *cross over*!

FU0 LO -> L0 left  if Addr[4] == 0  else L0 right
FU0 HI -> L0 right addr 4 will be 1 else L0 right

this has the strong disadvantage of not keeping the addresses that
we *know* have the same bits in the upper parts [12:48].

the other way to do it therefore is for the L0 to be only 8 rows
deep, comprising *two* 128-bit entries, i.e. to be integrated
L0-odd and L0-even where previously it was two separate L0 caches.

two L1 caches would then connect to that.

i'll think it through.

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