[libre-riscv-dev] [Bug 216] LOAD STORE buffer needed

[bugzilla-daemon@libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=216

--- Comment #20 from Luke Kenneth Casson Leighton <lkcl@lkcl.net> ---
the other thing, an aspect of the memory hazard and addr matching matrices:

* loads are separated completely from stores
* stores likewise
* atomic memory operations likewise (by marking them as both LD *and* ST)
* the *batch* order is what is preserved
* only one atomic ever gets sent through (batch of QTY 1).
* due to the expansion of the last 4 bits into a bitmap as part of addr_match,
no operations in any one "batch" will have overlapping bytes.  ever.

therefore there is no need - at all - to preserve "order" in any way shape or
form (hence why i said that we do not need a "queue" per se, we need more a L0
Cache/buffer).

(this wording - L0 cache/buffer - came out of the discussion on comp.arch with
Ivan. 8 entries is likely to be sufficient for us)

to emphasise:

* *at no time* will the DMs put out a mixed batch of LDs, STs or Atomics.
* acknowledging, clearing and completing each batch before moving onto the next
is absolutely critical.
* except for IO and Atomics (which will only be sent down one at a time anyway)
the order of LDs (or STs) can be entirely arbitrary.

also we can get away with full IO memory order preservation by treating them as
"Atomic".  this will result in them only being sent one at a time, in strict
order.

if the exact same dependency system were used at the L2 layer we could do full
SMP TSO with no difficulty.

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