From: bugzilla-daemon@libre-soc.org
To: libre-riscv-dev@lists.libre-riscv.org
Subject: [libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
Date: Mon, 18 May 2020 01:40:12 +0000
Message-ID: <bug-305-13-91teSWRIpr@https.bugs.libre-soc.org/> (raw)
In-Reply-To: <bug-305-13@https.bugs.libre-soc.org/>
https://bugs.libre-soc.org/show_bug.cgi?id=305
--- Comment #78 from Luke Kenneth Casson Leighton <lkcl@lkcl.net> ---
michael i am going to do a codeshuffle moving all pipelines to a subdir called
pipe.
common code can sit at that level including a README, as well as the multi
inout construction (based on the ReservationStation class).
also at that level would be a specification object that constructs multiple
Function Units just like in the diagram from Mitch's book.
some of these will be multiple pipes (the ones that only do one clock) and some
will be N > 1 ReservationStations but only the one pipe (DIV in particular)
also then in front of those will be the relevant CompUnits, some of which we
need to construct. ALUCompUnit will be the basis for most of them.
it starts with moving the pipelines to a pipe subdir, the rest needs its iwn
bugreport.
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2020-05-08 15:17 [libre-riscv-dev] [Bug 305] New: " bugzilla-daemon
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