[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py

[bugzilla-daemon@libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=305

--- Comment #7 from Luke Kenneth Casson Leighton <lkcl@lkcl.net> ---
(In reply to Michael Nolan from comment #5)

> > Those 4 batches of Function Units are *completely separate*.  they do
> > *NOT* interact.
> Oh ok. So essentially we will have *separate* ports for the addition pipe,
> the multiplication pipe, the branch pipe, and instructions can be issued to
> each in parallel. 

yeeees :)

now you're getting it.

the DMs preserve the register-usage order and manage the regfile Buses.

the only "stalling" that's done is when the Issue stage cannot find a free
ReservationStation row to reserve for the instruction.

the output from the pipeline goes into the RS row "output" latch and sits
there until the FunctionUnit says "DMs say we have a free and clear path
to write to the regfile: go... like... go NOW".

the more regfile ports you have, the more results get written in parallel.

likewise for regfile reads for getting the operands *into* the RS Row(s).

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