[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py

[bugzilla-daemon@libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=305

--- Comment #37 from Michael Nolan <mtnolan2640@gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #33)
> i haven't committed it (i leave it to you to evaluate)
> this passes the tests nosetests3 decoder/isa/test_caller.py 
> 
> register RA is read in - however it's not involved in the datapath for RB.
> 
> here's the pseudocode 
> 
> * rlwinm RA,RS,SH,MB,ME (Rc=0)
> * rlwinm.  RA,RS,SH,MB,ME (Rc=1)
> 
>     n <- SH
>     r <- ROTL32((RS)[32:63], n)
>     m <- MASK(MB+32, ME+32)
>     RA <- r & m
> 
> * rlwnm RA,RS,RB,MB,ME (Rc=0)
> * rlwnm.  RA,RS,RB,MB,ME (Rc=1)
> 
>     n <- (RB)[59:63]
>     r <- ROTL32((RS)[32:63], n)
>     m <- MASK(MB+32, ME+32)
>     RA <- r & m
> 
> the only difference is in n
> 
> both are 5 bit, SH should be coming from the immediate-decoding, (RB)[59:63]
> means get the 5 LSBs of RB.
> 
> i believe we're ok making the change below.  it doesn't make sense that IBM
> would design something that needs a special exception path for the immediate,
> just for one instruction.


Look at rlwimi:

n <- SH
r <- ROTL32(RS[32:63], n)
m <- MASK(MB+32, ME+32)
RA <- r & m | (RA) & ~m

It definitely does require reading in RS, RA, and SH

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