[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py

[bugzilla-daemon@libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=305

--- Comment #19 from Luke Kenneth Casson Leighton <lkcl@lkcl.net> ---
ok as it's "pass-through", i added so (and a comment) to main_stage.
also added some similar comments (and pass-through of so) on
input_stage.

diff --git a/src/soc/alu/main_stage.py b/src/soc/alu/main_stage.py
index e801c96..07fb018 100644
--- a/src/soc/alu/main_stage.py
+++ b/src/soc/alu/main_stage.py
@@ -39,7 +39,9 @@ class ALUMainStage(PipeModBase):
             with m.Case(InternalOp.OP_XOR):
                 comb += self.o.o.eq(self.i.a ^ self.i.b)

+        ###### sticky overflow and context, both pass-through #####
+        comb += so.eq(self.i.so)
         comb += self.o.ctx.eq(self.i.ctx)

         return m

about this:

class ALUOutputStage(PipeModBase):
    def __init__(self, pspec):
        super().__init__(pspec, "output")

    def ispec(self):
        return ALUOutputData(self.pspec)

    def ospec(self):
        return ALUOutputData(self.pspec)

if ALUOutputSpec is designed to generate ov, ov32, cr0 in *this*
stage (final one), then an ALUIntermediateData is needed
which does not have ov, ov32 or cr0 (etc.) in it.

-- 
You are receiving this mail because:
You are on the CC list for the bug.
_______________________________________________
libre-riscv-dev mailing list
libre-riscv-dev@lists.libre-riscv.org
http://lists.libre-riscv.org/mailman/listinfo/libre-riscv-dev