From: bugzilla-daemon@libre-soc.org
To: libre-riscv-dev@lists.libre-riscv.org
Subject: [libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
Date: Sat, 09 May 2020 13:45:26 +0000
Message-ID: <bug-305-13-Er3TsQVLz1@https.bugs.libre-soc.org/> (raw)
In-Reply-To: <bug-305-13@https.bugs.libre-soc.org/>
https://bugs.libre-soc.org/show_bug.cgi?id=305
--- Comment #17 from Luke Kenneth Casson Leighton <lkcl@lkcl.net> ---
(In reply to Michael Nolan from comment #14)
> We still need a carry_in from XER for things like add with carry.
just to check, XER is a Condition Register, right?
we may almost certainly need to split out the *individual* fields of XER and
other Condition Registers into actual separate "registers", even though they
are one or two bits.
the reason is because if we do not it will create artificial dependency
barriers between instructions that read or write some part of XER but not
another.
therefore all of CR0-CR7 need to be *different* "operands", likewise OV32, OV
and so on.
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